There are many applications for analog-to-digital converters. Real world analog information must be converted into a digital form before it can be processed by digital computers. There are a number of types of analog-to-digital converters employing various conversion methods. Each of these methods offer different performance characteristics such as operating speed, power consumption, achievable accuracy, chip area, required amplifier gain, bandwidth, impedance matching and noise.
Conventional electronic systems often package analog-to-digital converters (ADCs) on a separate integrated circuit. Generally, increased electronic integration offers a number of advantages. Hence it is desirable to integrate ADCs onto existing integrated circuit chips. This would reduce the total mass, volume, and system power, as well as the number and volume of power supplies in many systems. An indirect benefit would be a lowering of system design time and design error rate.
One example of an application for such integrated analog-to-digital converters is in the field of semiconductor imagers. There have been recent efforts to implement on-chip ADC onto detector arrays, such as focal-plane arrays (FPAs). Typically, signal chains introduce noise in focal-plane arrays. Therefore, besides the abovedescribed advantages of integrating ADCs, an FPA system with an on-focal-plane (on-chip) ADC would be expected to exhibit superior noise performance. This is due to the inevitable introduction of unwanted noise through cross-talk, clock pickup, power supply noise, electromagnetic interference (EMI) and other mechanisms. Since the serial data rate in the signal chain is typically the highest rate in the entire imaging system, white noise is introduced with a maximum bandwidth. Clock noise and other capacitively-coupled sources are also known to increase with increasing data rates.
On-chip ADCs would operate at a significantly lower bandwidth, ameliorating these effects. Since no off-chip analog cabling is required, pick up and vibration sensitivity would also be eliminated. More fundamentally, multiple sampling, or over-sampling, of the detector signal can be much more effectively performed on the focal plane compared to off-chip. Thus, on-chip ADC would eliminate mechanisms for the introduction of noise, as well as permit increased signal-to-noise ratio through over-sampling techniques. On-focal-plane ADC can also lead to a reduction in total FPA power dissipation.
Furthermore digital signals can be digitally processed on-chip as a further level of integration. For example, on-chip digital signal processing can be used for autonomous sensor control, e.g. exposure control, or for control, of windowed region-of-interest readout. Image compression can also be achieved on-chip to reduce off-chip drive requirements.
The incorporation of high resolution ADCs on focal-plane arrays has proved to be a difficult challenge. There is much less silicon area available on focal-plane arrays than there is on stand-alone ADCs. An ADC with serial architecture would be required to operate with the highest bandwidth of all focal-plane components, since the conversion rate would be the same as the pixel data rate. In a scientific application, a typical pixel data rate is about 100 KHz. In defense applications and in certain scientific applications, data rates in excess 100 MHz are often required. The power dissipation of CMOS at such high data rate circuits is also a concern.
These problems are compounded in scientific applications which routinely require resolutions greater than sixteen bits. This level of resolution generally requires over-sampling techniques that drive the ADC clock rate even higher. On-chip ADCs would also increase focal-plane power dissipation because of the required high speed operation of several analog circuits; compared to the single driver amplifier used in conventional focal-plane readouts. For these reasons, the inventors believe that a serial on-focal-plane ADC architecture would not be optimal.
Another alternative is a massively parallel architecture; for example, with one ADC on each readout pixel in the focal-plane array. However, only a relatively small area is available for most applications; typical pixel size is about 30 .mu.m.sup.2. Thus, this does not leave enough room for conventional ADC approaches which require a relatively large chip area.
In summary, speed limitations in serial architectures and area limitations in parallel architectures have restricted the implementation of on-focal-plane ADCs. The present inventors have recognized that the use of a semi-parallel architecture can be expected to preserve the advantages, and mitigate the adverse consequences, of both of these architectures. A semi-parallel architecture would, for example, utilize an ADC for every column of the readout. This affords virtually unlimited chip area in one dimension and tight, but feasible, design space in the other dimension. Such tall, skinny, ADCs would operate, in parallel, on one row of image data at a time.
A number of ADC techniques are available for use in focal-plane applications. These conversion methods differ from each other in terms of operating speed, power consumption, achievable accuracy, and chip area. An important difference between on-focal-plane ADC and a single chip monolithic ADC, is that an on-focal- plane ADC must occupy a relatively small chip area. The real estate becomes an even more serious concern for column-parallel approaches. Due to the unavailability of a large chip area, focal-plane ADCs cannot usually take advantage of elaborate trimming techniques for resolution enhancement. Thus, the immunity of the ADC performance to circuit parameter mismatch is a problem.
Low power operation is preferred in focal-plane ADCs. Maximum overall power dissipation in the combined ADCs would typically be limited to one to 20 mW. The required resolution and conversion rates vary widely depending upon applications. The conversion rate depends on the array size, the integration time, and the choice of ADC architecture, and is usually in the range of 1 KHz to 1 MHz. Scientific infrared imagers usually demand high resolution (greater than sixteen bits), but several other applications require only eight to ten bit accuracy. Thus there is a wide range of operating requirements. Conversion rate requirements vary from 1 KHz to 1 MHz, and the bit resolution requirements vary from six to over sixteen bits. There does not appear to be a single ADC algorithm that optimally meets all of these widely varying requirements.
Candidate ADC algorithms which meet some of these constraints include flash ADCs, successive approximation ADCs, single/dual slope ADCs, and over-sampled delta-sigma ADCs. For ADC operation in the two to ten bit range, the inventors have recognized that the successive approximation ADC is an attractive alternative for focal-plane applications. This kind of ADC achieves high resolution at medium speeds and with minimal power dissipation. One advantage with successive approximation is that for n bits, only n comparisons need to be made. This results in high speed and low power dissipation. Furthermore, this architecture does not require excessive chip area.
The successive-approximation analog-to-digital conversion process is essentially a "ranging" algorithm. Each conversion step estimates the upper and lower bound within which the input voltage lies. The analog voltage is approximated to within a small error by successively shrinking these bounds. The ranging can be done in several ways. One successive-approximation algorithm that is compatible with CMOS implementation is described in S. Ogawa, et al., "A switch-capacitor successive-approximation A/D converter", IEEE Trans. Instrum. and Meas., Vol. 42, pp. 847-853, 1993. One disadvantage with that approach is that the residual voltage decimates to approximately V.sub.ref /2.sup.n after n conversion steps. As a result, the ADC can be susceptible to circuit noise, offset and non-idealities.
It is hence an object of the present invention to overcome these disadvantages in order to realize many potential advantages of on-focal-plane ADC. It is also an object of the invention to provide an ADC which requires minimal chip area and power consumption. This is done according to the present invention by providing a successive approximation ADC that employs a capacitively-coupled multiplying digital to analog converter ("CCMDAC") to generate comparison voltage. This CCMDAC receives a plurality of input bits from a digital register. These input bits are coupled to capacitors that are weighted in powers of two. The output of the CCMDAC then depends on which input bits are on. The CCMDAC is an extremely low power digital to analog converter that generates a succession of comparison voltages for implementing the successive approximation algorithm of the analog-to-digital converter of the invention.
The capacitively-coupled successive approximation analog-to-digital converter of the invention includes a comparator that receives two inputs: one is the analog voltage input to be digitized; and the other is the CCMDAC output. The state of the digital register in the CCMDAC is controlled by a logic circuit that senses the output of the comparator indicating which of the two inputs is larger.
The digital register is initially set to be all zeros. The most significant bit (MSB) is then toggled and the first comparison is made. If the comparison shows that the CCMDAC output (V.sub.MDAC) is greater than the analog input (V.sub.in), then the MSB is set is to zero. The next significant bit is toggled and a new comparison is made. Again, if the V.sub.MDAC is greater V.sub.in, that bit is set to zero. Otherwise, it is set to one. This process is repeated for n bits. During each iteration, the output of the capacitively-coupled multiplying digital to analog converter increments by a successively smaller amount (such as one-half) due to the coupling of additional, sequentially smaller, capacitors within it. This process is repeated for n bits. The result of n comparisons is n-bits of resolution.
Another embodiment of the invention uses a double sided converter to accommodate a differential input. This embodiment can improve the common-non-ideality mode rejection of the comparator. This embodiment couples each comparator input to a circuit comprising a CCMDAC, digital register, and logic circuit, as described in the previous embodiment. The two sides of the differential input are now used as clamp signals to upper and lower CCMDACs. One digital register holds the converted value and the other its two's complement value. This embodiment works for both positive and negative input signals; the first bit is interpreted as a sign bit. Offset can be digitally compensated by setting the input voltage to zero (both sides equal) and storing the results in digital output.